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The CORE-V MCU DevKit is a turnkey, open-source development and prototyping platform for the CORE-V MCU System on Chip. The CORE-V MCU DevKit enables makers of IoT and embedded systems to evaluate the performance of the CORE-V MCU, to interconnect with WiFi and the IoT cloud, and to develop and test software using the CORE-V SDK.
Estimated Shipping Date: June 19, 2024
The CORE-V MCU DevKit is supported by OpenHW Group’s open-source CORE-V MCU SDK. The SDK comprises the following features
The CORE-V MCU SDK Quickstart Guide includes links and instructions to download and bring up the SDK on Linux and Windows.
OpenHW Group is a not-for-profit, global organization registered in Canada and driven by its members and individual contributors where HW and SW designers collaborate in the development of open-source cores, related IP, tools and SW such as the CORE-V Family of open-source RISC-V cores.
This campaign is a special collaboration with OpenHW Group and GroupGets. We're excited about being the newest member of the group to help bring about more new products powered by CORE-V, created by OpenHW Group. We coordinated with the OpenHW team to manage the manufacturing and test of sample units designed by Amazon.
The architecture of the DevKit is shown below:
Let’s review the main features of the DevKit, starting with the CORE-V MCU.
At the heart of the DevKit is the CORE-V MCU, an ASIC developed by the OpenHW community and fabricated in Global Foundry’s 22FDX process. The CORE-V MCU provides an evaluation and development platform for OpenHW’s fully-verified CV32E40PV1.0 embedded-class processor core. The CORE-V-MCU integrates the processor core with a set of on-chip peripherals, memory, and Quicklogic’s embedded FPGA (eFPGA) technology. The CORE-V MCU logic, with the exception of the eFPGA, is available on Github in open-source RTL under the permissive Solderpad 2.1 license.
The CV32E40P processor core is the first core released by OpenHW Group on Github in open-source RTL. It is a 4-stage, in-order 32-bit RISC-V processor core. The CV32E40P, developed through the collaborative efforts of the OpenHW community, is completely open-source and released under the permissive Solderpad 2.1 license. The ISA of CV32E40P as instantiated within the CORE-V-MCU supports the following instructions:
A block diagram of the CV32E40P core is shown below.
The CORE-V MCU includes 512K-byte of on-chip SRAM. The memory is organized as two 32K-byte banks of non-interleaved SRAM, typically used for program store, plus four 112K-byte banks of interleaved SRAM, typically used for data store. The interleaved memory architecture provides high speed access to memories for both the processor core and I/O peripherals.
The CORE-V MCU includes the following peripherals:
The embedded FPGA (eFPGA) subsystem integrated within the CORE-V MCU is based on Quicklogic’s ArcticPro 2 architecture. This is a silicon-verified, production-proven eFPGA for MCU/SoC/custom ASIC applications. The eFPGA IP enables the flexibility to easily program custom functions, hardware accelerators and security algorithms after an SoC has been manufactured. Programming the eFPGA within CORE-V MCU will be supported by Open Source tools to create the bitstream. Example designs will be provided.
The CORE-V MCU DevKit includes Espressif’s AWS IoT ExpressLink module, which provides WiFi and out-of-the-box, seamless connectivity to the AWS IoT ExpressLink cloud service. This allows DevKit-based IoT applications, such as the OpenHW-developed temperature sensing demonstration to interconnect with AWS IoT cloud services.
The CORE-V MCU DevKit includes a mikroBUS™ socket, comprising a pair of 1×8 female headers that support interconnection to a wide range of display, sensor, actuator and other modules.
The CORE-V MCU DevKit supports on-chip debugging of the CORE-V MCU via a JTAG interface and board connector. Additionally, the debug signals are converted to USB via the Ashling Opella-LD debug probe and brought out on USB-C.
The CORE-V MCU DevKit provides a 4 MB flash memory used to store program code and other data. In the case of program code, a CORE-V MCU ROM-based bootloader loads the flash memory into the CORE-V MCU internal 512 KB SRAM.
The CORE-V MCU DevKit supports a Himax camera (Ultra Low Power CMOS Image Sensor) connected to the CORE-V MCU via Camera Serial Interface. The camera is mounted on a flex cable that allows the user to orient the camera in a variety of directions.
The CORE-V MCU DevKit includes a switching power supply which can accept 5V from the USB-C, or 5V - 18 V from the 2.1 mm barrel connector.
One CORE-V MCU Devkit
Campaign Unsuccessful, ends when minimum unit count reached
14 Days after campaign end date
The CORE-V MCU Devkit can be powered from the 2.1mm barrel jack with 5-18V DC.
Use a USB-C cable to power and interface with the CORE-V MCU Devkit.
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